교수소개

부교수

나태희
직책/직급
부교수
주전공
반도체 집적회로 설계
담당과목
회로이론, 회로망이론, VLSI설계
전화번호
032-835-8452
이메일
taehui.na@inu.ac.kr
홈페이지
https://sites.google.com/view/svclab
학력

2017.02.27 연세대학교  (공학박사)

2012.02.27 연세대학교  (공학사)

경력

2024.03 인천대학교 전자공학부 반도체융합전공 (전공주임)

2023.10 인천대학교 지능형반도체공학과 (학과장)

2023.09 인천대학교 전자공학과 (부교수)

2019.09 ~ 2023.08 인천대학교 전자공학과 (조교수)

2017.03 ~ 2019.08 삼성전자 메모리사업부 (책임)

연구실적
<논문> 

STT-MRAM 기반 PUF의 한계점 분석 및 개선 전략, 전자공학회논문지 , 제62권(집) , 제5호 , PP.8~17 , 2025.05.01

Offset-tolerant body-biased sense amplifier with rise-time control technique for SRAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제72권(집) , 제5호 , PP.773~777 , 2025.05.01

Cost-effective, scalable UV-assisted SWCNT-based on-chip microsupercapacitors with high-performance leak-proof characteristics, CARBON , 제234권(집) , 2025.03.05

Area-optimized and reliable computing-in-memory platform based on STT-MRAM, Journal of Semiconductor Technology and Science , 제25권(집) , 제1호 , PP.56~65 , 2025.02.01

Analysis of low area digital up/down clipping counter for digital in-memory computing, IEEE Access , 제13권(집) , PP.32808~32818 , 2025.01.20

Tin sulfide dendritic hybrids enhanced by metallic carbon nanotubes for superior supercapacitor performance, Journal of Alloys and Compounds , 제1010권(집) , 2025.01.05

Spin current enhancement using double-ferromagnetic-layer structure for magnetoelectric spin-orbit logic device, Electronics , 제13권(집) , 제20호 , 2024.10.17

High-performance sum operation with charge saving and sharing circuit for MRAM-based in-memory computing, Journal of Semiconductor Technology and Science , 제24권(집) , 제2호 , PP.111~121 , 2024.04.01

Spin-transfer-torque magnetic-tunnel-junction-based low-power nonvolatile flip-flop designs in the subthreshold voltage region, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제31권(집) , 제10호 , PP.1565~1577 , 2023.10.01

Offset-canceling current-latched sense amplifier with slow rise time control and reference voltage biasing techniques, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 제70권(집) , 제7호 , PP.2689~2699 , 2023.07.01

Ternary output binary neural network with zero-skipping for MRAM-based digital in-memory computing, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제70권(집) , 제7호 , PP.2655~2659 , 2023.07.01

A timing-based split-path sensing circuit for STT-MRAM, Micromachines , 제13권(집) , 제7호 , 2022.07.01

Hierarchical formation of Ni sulfide single walled carbon nanotubes heterostructure on tin-sulfide scaffolds via mediated SILAR process: application towards long cycle-life solid-state supercapacitors, CERAMICS INTERNATIONAL , 제45권(집) , 제12호 , PP.16656~16666 , 2022.06.15

Study on cross-coupled-based sensing circuits for nonvolatile flip-flops operating in near/subthreshold voltage region, Micromachines , 제12권(집) , 제10호 , 2021.10.01

Body-biasing-based latch offset cancellation sensing circuit for deep submicrometer STT-MRAM, Journal of Semiconductor Technology and Science , 제21권(집) , 제2호 , PP.126~133 , 2021.04.01

STT-MRAM sensing: a review, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제68권(집) , 제1호 , PP.12~18 , 2021.01.01

Analysis of state-of-the-art spin-transfer-torque nonvolatile flip-flops considering restore yield in the near/sub-threshold voltage region, Electronics , 제9권(집) , 제12호 , 2020.12.11

Two dimensional, sponge-like In2S3 nanoflakes aligned on nickel foam via one-pot solvothermal growth and their application toward high performance supercapacitors, MATERIALS LETTERS , 제279권(집) , 2020.11.15

Novel MTJ-based sensing inverter variation tolerant nonvolatile flip-flop in the near-threshold voltage region, IEEE Access , 제8권(집) , PP.191057~191066 , 2020.10.20

Directly grown two dimensional In2S3 nanoflakes via one-step solvothermal method: material properties on In2S3 and performance data for supercapacitors, Data in Brief , 제32권(집) , PP.106272~ , 2020.10.01

Robust offset-cancellation sensing-circuit-based spin-transfer-torque nonvolatile flip-flop, IEEE Access , 제8권(집) , PP.159806~159815 , 2020.09.01

Robust offset-cancellation sense amplifier for an offset-canceling dual-stage sensing circuit in resistive nonvolatile memories, Electronics , 제9권(집) , 제9호 , 2020.09.01

Distribution analysis and multiple-point tail fitting yield estimation method for STT-MRAM, Journal of Semiconductor Technology and Science , 제20권(집) , 제3호 , PP.271~280 , 2020.06.01

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제27권(집) , 제11호 , PP.2548~2555 , 2019.11.01

Data-cell-variation-tolerant dual-mode sensing scheme for deep submicrometer STT-RAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 제65권(집) , 제1호 , PP.163~174 , 2018.01.01

A 10T-4MTJ nonvolatile ternary CAM cell for reliable search operation and compact area, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제64권(집) , 제6호 , PP.700~704 , 2017.06.01

Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65-nm CMOS, IEEE JOURNAL OF SOLID-STATE CIRCUITS , 제52권(집) , 제2호 , PP.496~504 , 2017.02.01

Multiple-cell reference scheme for narrow reference resistance distribution in deep submicrometer STT-RAM, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제24권(집) , 제9호 , PP.2993~2997 , 2016.09.01

Corner-aware dynamic gate voltage scheme to achieve high read yield in STT-RAM, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제24권(집) , 제9호 , PP.2851~2860 , 2016.09.01

Read disturbance reduction technique for offset-canceling dual-stage sensing circuits in deep submicrometer STT-RAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2016.06.01

An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제24권(집) , 제4호 , PP.1361~1370 , 2016.04.01

A double-sensing-margin offset-canceling dual-stage sensing circuit for resistive nonvolatile memory, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제62권(집) , 제12호 , PP.1109~1113 , 2015.12.01

Latch offset cancellation sense amplifier for deep submicrometer STT-RAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 제62권(집) , 제7호 , PP.1776~1784 , 2015.07.01

Reference-scheme study and novel reference scheme for deep submicrometer STT-RAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 제61권(집) , 제12호 , PP.3376~3385 , 2014.12.01

An offset-canceling triple-stage sensing circuit for deep submicrometer STT-RAM, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제22권(집) , 제7호 , PP.1620~1624 , 2014.07.01

A split-path sensing circuit for spin torque transfer MRAM, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 제61권(집) , 제3호 , PP.193~197 , 2014.03.01

Comparative study of various latch-type sense amplifiers, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 제22권(집) , 제2호 , PP.425~429 , 2014.02.01